A 8-Bit 8GSs Hierarchical Time-interleaved Multi-Bit SAR ADC with Digital Error Correction

Abstract

Due to the advanced noise-proof transmission characteristics of digital signal and the convenience brought digital signal processing, digital applications are expending exponentially. However, the world is analog, and the raw data and signals acquired for further processing or storage are analog as well. To perform digital process on those data and signals, analog-to-digital converters (ADC) are desired.

With the demand of high speed communication systems and high speed real-time control systems, such as broadband satellite communication systems, radar systems, broadband cable receivers and electronic back-end of optical cable receivers, high speed ADCs with moderate and/or conservative resolutions become a hot topic in ADC related research. In addition, low power consumption is a plus to the ADC to make it possible to be driven by batteries while maintain an acceptable battery life. With all these considerations, successive approximation register (SAR) based ADCs stands out with the benefits of technology down scaling to achieve a high sampling rate in GHz range with moderate resolution (6-10 bits) and relatively low power consumption. Serval ADCs in this specification range are reported recently, such as [1] and [2] with advanced technology (32nm SOI and 28nm UTBB FDSOI)

In this project, an 8 GS/s 8 Bit Hierarchical Time-Interleaved Multi-Bit SAR ADC with Digital Error Correction is designed with 28nm standard CMOS technology. To achieve the target sampling rate, time-interleaving structure is used to relax time window of conversion, while bring extra challenges to sampling front-end. Time-interleaved sampling front-end with interleaving factor M requires M clock signals with precise phases to ensure a uniform sampling in between channels. And jitter of each clock phases should also be well controlled to guarantee sampling accuracy.

And without the advantage of SOI technology used by [1][2], desired sampling bandwidth could not be achieved by a simple NMOS sampling switch. With all these consideration, a hierarchical time-interleaved structure with channel selection enabled bootstrap sampling switch in master hierarchy is proposed. And a 55Db sampling SNDR is achieved.

Unlike the single bit logic circuit, two bit per cycle logic circuit needs two extra comparators to split the reference voltage interval. Therefore, the noise caused by the comparator will be tripled than before. In order to achieve the same SNDR performance, the resolution of comparator needs to be increased. Besides, the design targets at quite high speed, thus the time used for comparison is limited. Thence, the comparator used in this design is required to have high resolution as well as high speed. The architecture used in the design is a double tail comparator combined with a pre-amplifier having regeneration part. The double tail comparator has higher gain formed by the input pair MOSFET, and the different clock signals provide extra current paths to expand the amplification time, so the speed sensitivity over the input voltage difference and noise performance are improved. As for the pre-amplifier, due to the help of different clock signals, the requirements on gain and linearity are not that critical. The difference between the two input signals just needs to be magnified three or four times, in this way, the pre-amplifier uses the basic common mode amplifier architecture with not large size MOSFET, which can avoid the effect of kickback noise and loading effect as well. During the regeneration period, the output of the pre-amplifier (input of the comparator) will be reset to Vdd. Hence, the input pair of comparator will be in saturation state when the comparing signal comes. Another problem may affect the accuracy of the comparator is the common mode voltage variation. To solve this problem, the Vcm-based switching method is applied.

The designed ADC operates under quite high speed, the total conversion time is limited. Compared with the single bit circuit, the two bit per cycle logic circuit will save much time as the conversion cycles is halved. However, during each conversion cycle of the two bit per cycle logic, more than one capacitor will be charged or discharged, besides, at least one of those charging or discharging capacitors has opposite movement compared with the others. So, each capacitor will have effect on the settling of the other capacitors. In this way, the top plate voltage may differ from the expected one, and the input signal cannot converge to Vcm. To avoid the error brought by the incorrect settling voltage, the redundant conversion step is added to the original process. The settling error in the former step will be compensated by the latter to ensure the signal voltage will finally converge to Vcm. Considering the tradeoff of effectiveness and complexity, the DAC array increases from 128C to 148C (C is the unit capacitor), thus the logic circuit can tolerate 15% settling error. In terms of speed, the dynamic logic is used instead of static logic to achieve high speed and lower power consumption. The digital error correction method is applied to transform the none-binary code into binary. [3]

[1] Kull, L., et al., "22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nmdigital SOI CMOS," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, vol., no., pp.378- 379, 9-13 Feb. 2014

[2] Le Tual, S., et al., "22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, vol., no., pp.382-383, 9-13 Feb. 2014

[3] J. H. Tsai et al., "A 0.003 mm 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching," in IEEE Journal of Solid-State Circuits, vol. 50, no. 6, pp. 1382-1398, June 2015